Resistive bridges are a major class of defects in nanometer technologies that can escape testing, posing a serious reliability risk for CMOS integrated circuits. The bridges generally result from undesired materials forming extraneous electrical connections in a circuit. FIG. 1 shows a distribution fit to the bridge resistance data for a typical fabrication process, where Rb is the bridging resistance and P(Rb) is the cumulative probability. This plot indicates that a substantial portion of bridge failures have a significant resistance (e.g., greater than 500 Ohms).
It is also known that as the power supply voltage Vdd is decreased, higher bridging resistances may be detected. In other words, faults that escape detection at higher values of Vdd may be detected when Vdd is dropped (i.e., fault coverage increases). Combined, these facts indicate that previous naïve assumptions of zero-Ohm bridge resistance models are insufficient for accurately determining bridge fault coverage. While this inaccuracy has been known and tolerated for some time in the digital fault simulation arena, it is less tolerable in the analog fault simulation arena. In analog circuitry, even small changes in a bridge resistance can make a big difference in its effect on the analog circuit behavior and thus in fault coverage.
More attention is therefore now being paid to resistive bridging, as shown by the emergence of resistive bridging fault simulators. These simulators focus on determining analog detectability intervals, which are the ranges of bridge resistances for which a given test pattern can detect a given fault.
At least one commercially available simulator tool provides an Analog Fault Sensitivity Analysis (AFSA), which is a technique for primarily establishing the detection status of defects. AFSA allows very efficient analog defect simulation with reasonable accuracy for transient analysis in nonlinear circuits. (Simulation generally includes mathematically applying selected stimuli to a circuit representation, and computing and outputting resultant circuit responses of interest, as is well understood in the art.) ASFA achieves much of its performance gain by simulating the presence of the analog faults only during short “refine time” intervals preceding the various test/measurement time points. For the remaining longer time intervals in between the test points, the fault-free or “golden” simulation waveforms and circuit states are re-used. This method generally succeeds when the fault-free solution to the circuit equations is reasonably close to the fault-in-place solution. (Note, the term “fault-free” simulation is a relative term. As a practical matter, there may be faults in a “fault-free” simulation, but the ordinarily skilled artisan will understand that the number of faults is small, and that the faults would not affect the overall operation of the simulation with respect to the relevant outputs that are the subject of the comparison.)
However, this simulator tool currently uses a single user-specifiable bridge resistance value per fault. As such, the tool is also somewhat naïve, and its fault coverage determination may suffer accordingly. It is however possible to determine analog circuit fault coverage versus bridge resistance value at the user level by performing multiple AFSA runs. A different bridge resistance parameter value would be specified for each simulation run.
FIG. 2 shows the results of such a brute force simulation performed for a given fault, called Fault 1. The simulation uses three different exemplary bridge resistance values, e.g., 1000 Ohms, 100 Ohms, and 10 Ohms, which represent a sampling of the known bridge resistance distribution of FIG. 1. Trace 200 corresponds to the fault-free circuit response, depicting a particular node voltage waveform of interest as a function of time, with voltages 210 and 212 occurring at times TP1 and TP2, respectively. The other traces (202, 204, and 206) show the circuit voltage response in the presence of the fault with each of the three different fault resistance values. For example, response 202 is the result for Fault 1 having a resistance of 1000 Ohms, response 204 is the result for Fault 1 having a resistance of 100 Ohms, and response 206 is the result for Fault 1 having a resistance of 10 Ohms. Typically, the circuit responses for various resistance values need to be determined at various specified test point times, such as TP1 (voltages 214, 216, and 218) and TP2 (voltages 224, 226, and 228) as shown. The simulation may begin at tstart, a selected start time (not necessarily zero).
FIG. 3 depicts the results of repeating the simulation for a second fault, called Fault 2. In this case, the simulator may determine three additional trajectories as shown in traces 302, 304, and 306. These traces show the circuit response in the presence of Fault 2 with the same three fault resistance values of 1000, 100, and 10 Ohms as before. Voltages 314, 316, and 318 occur at TP1 for the various resistance values, and voltages 324, 326, and 328 occur at TP2. Fault 2's circuit responses appear to be closer to the fault-free circuit response 200 when compared with the circuit responses with Fault 1. For example, at time point TP2, voltage 324 resulting from the 1000 ohm fault is essentially the same as fault-free voltage 212. The circuit operation is thus somewhat more tolerant of a resistive bridge with Fault 2, making fault detection more difficult for Fault 2.
A simulator or post-processing tool may “detect” faults in many different ways. In general, detection of a fault may involve performing various mathematical operations and transformations on circuit quantities to compute performance values, and comparing the computed performance values against expected values. For example, a fault may be detected if it causes a circuit node voltage or current to deviate from a fault-free voltage or current excessively. Faults may also be detected by comparing more involved circuit performance quantities, such as the frequency of a voltage or current oscillation. Alternatively, a detection voltage threshold or current threshold or a frequency range may be set, and comparisons made to detect faults. The comparisons may be simple comparisons with a threshold, or more complex comparisons such as whether values fit within a range. The range itself may even vary as a function of the test point. The specifics of the comparison may be circuit/application specific, and may vary from one type of circuit to the next.
In a simple example, the simulator may set or compute a detection threshold voltage, e.g. voltage 208, for use as a comparison. The detection threshold voltage may be related to the voltage required to cause a circuit malfunction. If a fault is considered “detected” for any value of the voltage response waveform below the detection threshold 208 shown for TP1 for example, then Fault 1 of FIG. 2 would be detected for all three fault values. However, Fault 2 of FIG. 3 would only be detected for the 100 Ohm and 10 Ohm cases. Fault 2 would not be detected at the 1000 Ohm case as its TP1 voltage value 314 is above the detection threshold value 208.
This analysis approach requires significant simulation time, which increases linearly with the number of runs (i.e., the number of different bridge resistance parameter values of interest), in order to represent a sufficient sampling of the range of resistance values known to occur. Since analog fault simulations are already notoriously slow, even with the efficiencies introduced by the AFSA technique, this multiple simulation approach to sample the resistive bridge values is prohibitive in terms of both CPU usage and disk usage. Therefore the circuit design industry requires a method to more efficiently calculate analog circuit responses and corresponding fault coverage in the face of multiple bridge resistance parameter values. Accordingly, the inventors have developed an efficient single-run method to determine analog fault coverage versus bridge resistance.